It is difficult to imagine any scientific computation without a floating-point arithmetic. Today's hardware costs have approached the point where a hardware implementation of a floating-point, arithmetic-logic unit is not only feasible but economically practical. In such a unit, a high-speed shifting network is a necessity for pre-normalization in unnormalized, floating-point, for arithmetic alignment of one of the mantissas in floating-point addition and subtraction, for post-normalization of the resultant mantissa in any normalized, floating-point operation, and for shifting partial results during the multiply and divide operations. The same network may be used for field manipulations such as extraction and isolation of fields during emulation of various machines, or insertion and transfer of fields during packing and unpacking.
Arithmetic operations require mostly right and left end-off shifts. Although every field manipulation can be obtained through a sequence of left and right end-off shifts and logical operations, a high-speed, arithmetic-logic unit requires a circular shift and masking capabilities to achieve speed of arithmetic operations in field-manipulation operations. On the other hand, todays standardized logic families are not well equipped with circuits that can be used as building blocks in design of left and right end-off shifters. Uniform shift networks that can shift an arbitrary number of places are usually implemented as one or more levels of multiplexers or selectors, see Davis, R. L., "Uniform Shifting Networks," Computer, 1974 Vol. 7, pp. 60-71, September 1974. Such a network is basically connected as a circular shifter with insertion of the proper number of zeroes (ones) on the left-most portion of the data word when right end-off shift is required and vice-versa when left end-off shift is required. Insertion of zeroes (ones) is distributed across the entire shifting network, and requires disabling of certain multiplexer outputs. The number of multiplexer outputs and their positions is different at each level and depends on shift amount and the direction of shifting. Further, it is not only difficult to determine the multiplexer outputs to be disabled, but also available MSI multiplexer packages do not provide an enable control for every output. If there is enable capability at all, it is applicable to all outputs.